View GS74116U-15_4167157.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev: 2 .0 2 3/2000 1/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u 256k x 16 4 mb asynchronous sram 8, 10, 12 , 15 ns 3.3v v dd center v dd & v ss soj, tsop , fp-bga commercial temp industrial temp features ? fast access time: 8, 10 , 12 , 15 ns ? cmos low power operation: 170/145/130/110 ma at min.cycle time. ? single 3.3v 0.3v power supply ? all inputs and outputs are ttl compatible ? byte control ? fully static operation ? industrial temperature option: -40 to 85c ? package line up j: 400mil, 44 pin soj package tp: 400mil, 44 pin tsop type ii package u: 7.20mm x 11.65mm fine pitch ball grid array package description the gs 741 16 is a high speed cmos static ram organized as 262,144 -words by 16 -bits. static design eliminates the need for exter- nal clocks or timing strobes. operating on a single 3.3v power supply and all inputs and outputs are ttl compatible. the gs 741 16 is avail- able in a 7.2x11.65 mm fine pitch bga package , 400 mil soj and 400 mil tsop type-ii package s . pin descriptions soj 256k x 16 pin configuration fine pitch bga 256k x 16 bump configuration 7.2x11.65mm 0.75mm bump pitch top view symbol description a 0 to a 17 address input dq 1 to dq 16 data input/output ce chip enable input lb lower byte enable input (dq1 to dq8) ub upper byte enable input (dq9 to dq16) we write enable input oe output enable input v dd +3.3v power supply v ss ground nc no connect 1 2 3 4 5 6 a lb oe a 0 a 1 a 2 nc b dq 16 ub a 3 a 4 ce dq 1 c dq 14 dq 15 a 5 a 6 dq 2 dq 3 d v ss dq 13 a 17 a 7 dq 4 v dd e v dd dq 12 nc a 1 6 dq 5 v ss f dq 11 dq 10 a 8 a 9 dq 7 dq 6 g dq 9 nc a 10 a 11 we dq 8 h nc a 12 a 13 a 14 a 15 nc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a 4 a 3 a 2 a 1 a 0 ce dq 1 dq 2 dq 3 dq 4 v dd v ss dq 5 dq 6 dq 7 dq 8 we a 15 a 14 a 13 a 5 a 6 a 7 oe ub lb dq 16 dq 15 dq 14 dq 13 v ss v dd dq 12 dq 11 dq 10 dq 9 nc a 8 a 9 a 10 top view 21 22 24 23 a 12 a 11 44 pin soj a 17 a 16
rev: 2 .0 2 3/2000 2/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u tsop-ii 256k x 16 pin configuration 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a 4 a 3 a 2 a 1 a 0 ce dq 1 dq 2 dq 3 dq 4 v dd v ss dq 5 dq 6 dq 7 dq 8 we a 15 a14 a 13 a 5 a 6 a 7 oe ub lb dq 16 dq 15 dq 14 dq 13 v ss v dd dq 12 dq 11 dq 10 dq 9 nc a 8 a 9 a 10 top view 21 22 24 23 a 12 a 11 44 pin tsop ii a 17 a 16 memory array row decoder column decoder address input buffer control i/o buffer a 0 ce we oe dq 1 a 17 block diagram dq 16 ub _____ lb _____
rev: 2 .0 2 3/2000 3/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u note: x: ?h? or ?l? note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation shall be restricted to recommen ded operating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. truth table ce oe we lb ub dq 1 to dq 8 dq 9 to dq 16 v dd current h x x x x not selected not selected isb 1 , isb 2 l l h l l read read i dd l h read high z h l high z read l x l l l write write l h write not write, high z h l not write, high z write l h h x x high z high z l x x h h high z high z absolute maximum ratings parameter symbol rating unit supply voltage v dd -0.5 to +4.6 v input voltage v in -0.5 to v dd +0.5 ( 4.6v max.) v output voltage v out -0.5 to v dd +0.5 ( 4.6v max.) v allowable power dissipation pd 0.7 w storage temperature t stg -55 to 150 o c
rev: 2 .0 2 3/2000 4/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u note: 1. input overshoot voltage should be less than v dd +2v and not exceed 20ns. 2. input undershoot voltage should be greater than -2v and not exceed 20ns. notes: 1. tested at t a =25c, f=1mhz 2. these parameters are sampled and are not 100% tested recommended operating conditions parameter symbol min typ max unit supply voltage for - 10/ 12/15 v dd 3.0 3.3 3.6 v supply voltage for - 8 v dd 3.135 3.3 3.6 v input high voltage v ih 2.0 - v dd +0.3 v input low voltage v il -0.3 - 0.8 v ambient temperature, commercial range t ac 0 - 70 o c ambient temperature, industrial range t a i -40 - 85 o c capacitance parameter symbol test condition max unit input capacitance c in v in =0v 5 pf output capacitance c out v out =0v 7 pf dc i/o pin characteristics parameter symbol test conditions min max input leakage current i il v in = 0 to v dd -1ua 1ua output leakage current i lo output high z v out = 0 to v dd -1ua 1ua output high voltage v oh i oh = - 4ma 2.4 output low voltage v ol i lo = + 4ma 0.4v
rev: 2 .0 2 3/2000 5/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u ac test conditions power supply currents parameter symbol test conditions 0 to 70c -40 to 85c 8ns 10ns 12ns 15ns 10ns 12ns 15ns operating supply current i dd ce v il all other inputs 3 v ih or v il min. cycle time i out = 0 ma 170ma 145ma 130ma 110ma 155ma 140ma 120ma standby current i sb1 ce 3 v ih all other inputs 3 v ih or v il min. cycle time 70ma 65ma 60ma 55ma 75ma 70ma 65ma standby current i sb2 ce 3 v dd - 0.2v all other inputs 3 v dd - 0.2v or 0.2v 30ma 40ma dq vt=1.4v 50 w 30pf 1 dq 3.3v output load 1 output load 2 589 w 434 w 5pf 1 note: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted 3. output load 2 for t lz , t hz , t olz and t ohz . parameter conditions input high level v ih =2.4v input low level v il =0.4v input rise time tr=1v/ns input fall time tf=1v/ns input reference level 1.4v output reference level 1.4v output load fig. 1& 2
rev: 2 .0 2 3/2000 6/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u ac characteristics * these parameters are sampled and are not 100% tested read cycle 1: ce = oe = v il , we = v ih , ub and, or lb = v il read cycle parameter symbol -8 -10 -12 -15 unit min max min max min max min max read cycle time t rc 8 --- 10 --- 12 --- 15 --- ns address access time t aa --- 8 --- 10 --- 12 --- 15 ns chip enable access time ( ce ) t ac --- 8 --- 10 --- 12 --- 15 ns byte enable access time ( ub , lb ) t ab --- 3.5 --- 4 --- 5 --- 6 ns output enable to output valid ( oe ) t oe --- 3.5 --- 4 --- 5 --- 6 ns output hold from address change t oh 3 --- 3 --- 3 --- 3 --- ns chip enable to output in low z ( ce ) t lz * 3 --- 3 --- 3 --- 3 --- ns output enable to output in low z ( oe ) t olz * 0 --- 0 --- 0 --- 0 --- ns byte enable to output in low z ( ub , lb ) t blz * 0 --- 0 --- 0 --- 0 --- ns chip disable to output in high z ( ce ) t hz * --- 4 --- 5 --- 6 --- 7 ns output disable to output in high z ( oe ) t ohz * --- 3.5 --- 4 --- 5 --- 6 ns byte disable to output in high z ( ub , lb ) t bhz * --- 3.5 --- 4 --- 5 --- 6 ns t aa t oh t rc address data out previous data data valid
rev: 2 .0 2 3/2000 7/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u read cycle 2: we = v ih * these parameters are sampled and are not 100% tested write cycle parameter symbol -8 -10 -12 -15 unit min max min max min max min max write cycle time twc 8 --- 10 --- 12 --- 15 --- ns address valid to end of write taw 5.5 --- 7 --- 8 --- 10 --- ns chip enable to end of write tcw 5.5 --- 7 --- 8 --- 10 --- ns byte enable to end of write tbw 5.5 --- 7 --- 8 --- 10 --- ns data set up time tdw 4 --- 5 --- 6 --- 7 --- ns data hold time tdh 0 --- 0 --- 0 --- 0 --- ns write pulse width twp 5.5 --- 7 --- 8 --- 10 --- ns address set up time tas 0 --- 0 --- 0 --- 0 --- ns write recovery time ( we ) twr 0 --- 0 --- 0 --- 0 --- ns write recovery time ( ce ) twr1 0 --- 0 --- 0 --- 0 --- ns output low z from end of write twlz * 3 --- 3 --- 3 --- 3 --- ns write to output in high z twhz * --- 3.5 --- 4 --- 5 --- 6 ns taa trc address tac tlz tab tblz toe tolz ce ub , lb oe data out thz tbhz tohz data valid high impedance
rev: 2 .0 2 3/2000 8/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u write cycle 1: we control write cycle 2: ce control twc address ce ub , lb we data in oe data out taw tcw tbw tas twp twr tdw tdh twlz twhz data valid high impedance twc address ce ub , lb we data in oe data out taw twp tas tcw twr1 tdw tdh data valid high impedance tbw
rev: 2 .0 2 3/2000 9/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u write cycle 3: ub , lb control twc address ce ub , lb we data in oe data out taw twp tas tcw twr1 tdw tdh data valid high impedance tbw
rev: 2 .0 2 3/2000 10/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u 44 pin, 400 mil soj 1 22 23 44 e b1 d a 1 a 2 y e h e q c l g e detail a a b a note: 1. dimension d& e do not include interlead flash 2. dimension b1 does not include dambar protrusion / intrusion symbol dimension in inch dimension in mm min nom max min nom max a - - 0.148 - - 3.759 a1 0.025 - - 0.635 - - a2 0.105 0.110 0.115 2.667 2.794 2.921 b - 0.018 - - 0.457 - b1 0.026 0.028 0.032 0.660 0.711 0.813 c - 0.008 - - 0.203 - d 1.120 1.125 1.130 28.44 28.58 28.70 e 0.395 0.400 0.405 10.033 10.160 10.287 e - 0.05 - - 1.27 - h e 0.435 0.440 0.445 11.049 11.176 11.303 g e 0.360 0.370 0.380 9.144 9.398 9.652 l 0.082 0.087 0.106 2.083 2.210 2.70 y - - 0.004 - - 0.102 q 0 o - 7 o 0 o - 7 o
rev: 2 .0 2 3/2000 11/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u 44 pin, 400 mil tsop-ii d 1 22 23 44 e b q a a 1 a 2 y c detail a e h e l l 1 a note: 1. dimension d& e do not include interlead flash 2. dimension b does not include dambar protrusion / intrusion 3. controlling dimension: mm symbol dimension in inch dimension in mm min nom max min nom max a - - 0.047 - - 1.20 a1 0.002 - - 0.05 - - a2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.01 0.014 0.018 0.25 0.35 0.45 c - 0.006 - - 0.15 - d 0.721 0.725 0.729 18.31 18.41 18.51 e 0.396 0.400 0.404 10.06 10.16 10.26 e - 0.031 - - 0.80 - h e 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.020 0.024 0.40 0.50 0.60 l1 - 0.031 - - 0.80 - y - - 0.004 - - 0.10 q 0 o - 5 o 0 o - 5 o
rev: 2 .0 2 3/2000 12/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u 7.2mmx11.65mm fp-bga pin a1 index a1 e top view side view d a aaa pin a1 index e1 bottom view d1 c e e solder ball f b symbol unit: mm a a1 f b f 0.35 c 0.36(typ) d d1 5.25 e e1 3.75 e 0.75(typ) aaa 0.10 1.100.10 0.220.05 7.200.10 a b c d e f g h 1 2 3 4 5 6 11.650.10
rev: 2 .0 2 3/2000 13/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u * customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. for example: gs 741 16 tp-10t ordering information part number * package access time temp. range status gs74116tp-8 400 mil tsop-ii 8 ns commercial gs74116tp-10 400 mil tsop-ii 10 ns commercial gs74116tp-12 400 mil tsop-ii 12 ns commercial gs74116tp-15 400 mil tsop-ii 15 ns commercial gs74116tp-8i 400 mil tsop-ii 8 ns industrial gs74116tp-10i 400 mil tsop-ii 10 ns industrial gs74116tp-12i 400 mil tsop-ii 12 ns industrial gs74116tp-15i 400 mil tsop-ii 15 ns industrial gs74116j-8 400 mil soj 8 ns commercial gs74116j-10 400 mil soj 10 ns commercial gs74116j-12 400 mil soj 12 ns commercial gs74116j-15 400 mil soj 15 ns commercial gs74116j-8i 400 mil soj 8 ns industrial gs74116j-10i 400 mil soj 10 ns industrial gs74116j-12i 400 mil soj 12 ns industrial gs74116j-15i 400 mil soj 15 ns industrial gs74116u-8 fine pitch bga 8 ns commercial gs74116u-10 fine pitch bga 10 ns commercial gs74116u-12 fine pitch bga 12 ns commercial GS74116U-15 fine pitch bga 15 ns commercial gs74116u-8i fine pitch bga 8 ns industrial gs74116u-10i fine pitch bga 10 ns industrial gs74116u-12i fine pitch bga 12 ns industrial GS74116U-15i fine pitch bga 15 ns industrial
rev: 2 .0 2 3/2000 14/14 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. n gs7 4 1 16 tp /j /u revision history rev. code: old; new types of changes format or content page #/revisions/reason rev1.03c 3/1999; 1.04d 6/1999 format/typos document/changed format of subscripts on pins to small caps. content 13/changed tape and reel note at end of ordering info./enhancement 1.04d 6/1999; 2.00 8/1999 format/typos none content 1. added fine pitch bga package to datasheet. 2. 10/added dimension ?d? to soj package diagram/was missing 3. 11/added dimension ?d? to tsop package diagram/was missing gs 741 rev 2.0 1 krev 2 1 2/2000l format/content 1. gsi logo 2. gs74116 rev2.01 2/2000l; rev 2.02 3/2000n content 1. changed pin a17 from 3e to 3d.

▲Up To Search▲

Price & Availability of GS74116U-15

	To Download GS74116U-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .